The present invention relates to an impedance matching circuit in a semiconductor memory device, and more particularly to a ZQ calibration performed by the impedance matching circuit.
Generally, semiconductor memory devices that include an integrated circuit such as a microprocessor, a memory circuit and a gate array circuit, are used in various electrical appliances, e.g., personal computers, server computers and workstations. As the operating speed of the electrical appliances increases, a swing width of signals transmitted between semiconductor memory devices inside the electrical appliances decreases to minimize a delay time taken to transmit the signals. However, as the swing width decreases, signal transmission is affected by external noise to a greater degree and signal reflection in an interface terminal increased due to impedance mismatching.
The impedance mismatch is caused by variation of the manufacturing process, the supply voltage and the operating temperature (PVT). This impedance mismatch makes it hard to transmit data at high speeds. Because a signal outputted from a semiconductor memory device may be distorted by the impedance mismatch, a malfunction such as a set up/hold failure or a misjudgment of a signal level may be caused in a corresponding semiconductor memory device receiving the distorted signal.
A semiconductor memory device may include an input circuit for receiving external signals through an input pad and an output circuit for outputting internal signals through an output pad. Particularly, a semiconductor memory device operating at a high speed may include an impedance matching circuit for matching interface impedance with another semiconductor memory device near the pads in order to prevent the above malfunctions.
Generally, in a semiconductor memory device transmitting a signal, source termination is performed by an output circuit. In a semiconductor memory device receiving a signal, parallel termination may be performed by a termination circuit parallelly connected to an input circuit.
The ZQ calibration is a process for generating pull-up and pull-down calibration codes that change as PVT conditions change. Resistance values of input and output circuits are calibrated by using the pull-up and pull-down calibration codes. The ZQ calibration performed in the impedance matching circuit is described below.
FIG. 1 is a block diagram of a conventional impedance matching circuit. The impedance matching circuit includes a first pull-up resistance unit 110, a second pull-up resistance unit 120, a pull-down resistance unit 130, a reference voltage generator 102, comparators 103 and 104, and p-code and n-code counters 105 and 106.
A supply voltage VDDQ is divided by the first pull-up resistance unit 110 and a reference resistor 101, thereby providing a voltage to a node ZQ. The reference resistor 101, which is connected to a pin coupled to the node ZQ, generally has a resistance of 240Ω. The comparator 103 compares the voltage at the node ZQ with a reference voltage VREF outputted from the reference voltage generator 102, thereby generating an up/down signal UP/DN. The reference voltage VREF is generally set to half of the supply voltage, i.e., VDDQ/2.
The p-code counter 105 receives the up/down signal UP/DN, thereby generating a binary code PCODE<0:N>. The binary code PCODE<0:N> turns on/off MOS transistors coupled in parallel in the first pull-up resistance unit 110, thereby calibrating resistance of the first pull-up resistance unit 110. The calibrated resistance of the first pull-up resistance unit 110 has an effect on the voltage at the node ZQ. The above operations are repeated. That is, the pull-up calibration is performed in the first pull-up resistance unit 110 so that the resistance of the first pull-up resistance unit 110 becomes identical to that of the reference resistor 101.
The binary code PCODE<0:N> generated during the pull-up calibration is also inputted to the second pull-up resistance unit 120 and determines its resistance. Similarly to the pull-up calibration, a pull-down calibration is performed. A voltage at a node ZQ′ becomes identical to the reference voltage VREF by applying a binary code NCODE<0:N> generated by the comparator 104 and the n-code counter 106. The pull-down calibration is performed so that the resistance of the pull-down resistance unit 130 becomes identical to that of the second pull-up resistance unit 120.
The ZQ calibration includes the pull-tip calibration and the pull-down calibration. The binary codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration are inputted to an input or output circuit so as to calibrate the respective resistance of the input or output circuit. In the case of the semiconductor memory device, the binary codes PCODE<0:N> and NCODE<0:N> determine the resistance of pull-up and pull-down resistors connected to ZQ pads. Since the pull-up and pull-down resistors have an identical layout to the above pull-tip and pull-down resistance units. illustrating their structures in the drawings is omitted.
While an output driver of the semiconductor memory device uses both pull-up and pull-down resistors, an input buffer of the semiconductor memory device uses only a pull-up resistor. In that case, the impedance matching circuit includes the pull-up resistance unit 110, the p-code counter 105 and comparator 103. Only the pull-up calibration is then performed.
The ZQ calibration prevents an impedance mismatch from occurring. However, the bandwidth of data transmitted by the semiconductor memory device is reduced as the operating time for the ZQ calibration is lengthened. Accordingly, the time for the ZQ calibration must be minimized to improve transmission efficiency of the data as well as prevent an impedance mismatch.